The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique which is effectively applicable to enhancement of electric characteristics of semiconductor devices.
With respect to a semiconductor package (semiconductor device), conventionally, a problem relating to reflow cracks has been known. As a method for solving such a problem, a small tab structure which sets a size of tabs (chip mounting portions) to a value smaller than a size of semiconductor chips has been proposed. As one example of the small tab structure, a QFP (Quad Flat Package) having a small tab structure has been known.
Further, with respect to the semiconductor package having a small tab structure, to enhance electric characteristics such as characteristics which can cope with high frequency, there exists a semiconductor package which is required to have stabilization of ground/power source potential. For example, such a technique is disclosed in Japanese Unexamined Patent Publication No. Hei. 11(1999)-168169.
Japanese Unexamined Patent Publication No. Hei. 11(1999)-168169 discloses a technique that in a QFP having a small tab structure, ground/power source connecting portions which are supported by tab suspending leads (suspending leads) are provided, and by connecting pads (electrodes) of the semiconductor chip with the ground/power source connecting portions using wires, restrictions imposed on a pad layout is eliminated and, at the same time, the stability of ground/power source potential is enhanced.
However, in the QFP, since the tab suspending leads are not exposed to a mounting surface of a sealing body, the tab suspending leads cannot be used as external terminals.
Accordingly, the use of outer leads is indispensable as ground/power source pins.
As a result, it is necessary to use some outer leads as the ground/power source pins out of a large number of outer leads thus giving rise to a problem that the number of pins for signals is decreased.
Recently, a tendency to use a large number of pins aiming at enhancement of functions of semiconductor package is increasing and hence, particularly with respect to the semiconductor package having large pins, the decrease of the number of pins for signals leads to a serious problem. Further, the stabilization of a ground/power source potential is also considered to be a serious task to be solved.
Accordingly, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof for achieving stabilization of a ground/power source potential without decreasing the number of pins for signals.
It is another object of the present invention to provide a semiconductor device and a manufacturing method thereof which can enhance electric characteristics thereof.
The above-mentioned objects and other objects and novel features of the present invention will become apparent from the description of this specification and attached drawings.
To describe the summary of typical inventions out of inventions disclosed in the present invention, they are as follows.
According to a first aspect of the present invention, there is provided a semiconductor device which includes a semiconductor chip which has a semiconductor die and a plurality of electrodes, a plurality of leads which are arranged around the semiconductor chip, a tab which has a size smaller than a size of a main surface of the semiconductor chip and is bonded to a back surface of the semiconductor chip, a plurality of suspending leads which are connected to the tab and to which bent portions are formed so as to form stepped portions with respect to the tab, common lead portions which are connected to the suspending leads and have at least portions thereof arranged outside the semiconductor chip, a plurality of first wires which electrically connect a plurality of electrodes of the semiconductor chip with a plurality of leads respectively, second wires which electrically connect electrodes of the semiconductor chip with the common lead portions, and a sealing body which seals the semiconductor chip, the first and the second wires, the tab and the common lead portion using resin, wherein a plurality of leads and a plurality of suspending leads have portions thereof exposed to a mounting surface of the sealing body, and a distance between a suspending lead exposing portion and a lead exposing portion disposed close to the suspending lead portion on the mounting surface is set to a value equal to or more than a distance between the neighboring lead exposing portions.
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor including a step of preparing a lead frame including a tab which has a size smaller than a main surface of a semiconductor chip, a plurality of leads, a plurality of suspending leads which are connected to the tab and common lead portions which are connected to the suspending leads, a step of adhering the semiconductor chip on which a plurality of electrodes are formed and the tab using an adhesive material, a step of electrically connecting the electrodes of the semiconductor chip and the common lead portions of the lead frame corresponding to the electrodes of the semiconductor chip by second wires, a step of electrically connecting the electrodes of the semiconductor chip and the leads of the lead frame corresponding to the electrodes of the semiconductor chip by first wires, a step of sealing the semiconductor chip, the first and second wires, the tabs and the common lead portions using resin in a state that the plurality of suspending leads of the lead frame are sandwiched by a first mold and a second mold of a forming mold and in such a manner that portions of the respective plurality of leads and suspending leads are exposed on a mounting surface of a sealing body, and a step of separating the plurality of leads and suspending leads from the lead frame.
In the method for manufacturing the semiconductor device, wire bonding is performed such that a wire loop of the first wire is set higher than a wire loop of the second wire.